As the complexity and number of components on a processing unit chip have increased, the difficulty in testing these chips has increased. One standardized test protocol is the JTAG (Joint Test Action Group) protocol. Referring to FIG. 1, in this test environment, a test and debug unit 5, in response to user inputs applies control and data signals to scan controller 10. The scan control formats the control and data signals and transfers these signals to the target processing unit, the unit under test. The target processing unit 15 performs the activity defined by the control signals and returns the results of the test procedure to the scan control unit 10 with a serial transfer of data. The scan control unit 15 reformats the test result signals from the target processing unit 15 and transfers these signals to the test and debug unit 5 for analysis.
Referring to FIG. 2, a block diagram of the scan controller is shown. The test and debug apparatus enters control signals for the scan controller 10 into the scan controller command register 11. The command register distributes control signals throughout the scan controller 10 to implement the test activity. The test and debug unit 5 also enters test and data signals into input register 12. The test and data signals are entered into the data generator. 14. The data generator 14 reformats the test and data signals and applies the reformatted signals to the target processing unit 8. Data generator 14 exchanges signals with the sequence generator 15. The sequence generator 15, in response to the signals exchanged with the data generator 14 and the control signals received from the command register 11, applies test mode signals to the target processing unit 8. The target processing unit 8, in response to the signals from the data generator 14 and the sequence generator 15, performs the test/debug procedure defined by the test and data signals. After execution of the activity defined by the test and data signals by the target processing unit 8, the results of the test procedure are transferred to the data generator 14. The test result procedure are reformatted and applied to the output register 17. The results of the test procedure are then transferred from the output register to the test and debug unit 5. The test results are then analyzed by the test and debug unit 5 to determine how to proceed with the testing of the target processor.
One common test procedure is “polling”. In polling, a value found at a selected location in the target processor is repeatedly examined until an expected value is found at that location. For each access of the selected location, the same signals much be transferred from the test and debug unit 5 to the scan controller 10 to be forwarded to the target processing unit 8. In addition, the value retrieved from the selected location must be transferred to the test and debug unit 5 to determine whether the expected value was found selected. Thus, the polling procedure requires extensive communication between the components of the testing apparatus. Each individual poll of the selected location requires multiple clock cycles before a determination is made whether the procedure must be repeated.
A need has been felt for apparatus and an associated method having the feature of improving the efficiency of the polling operation. It would be a further feature of the apparatus and associated method to provide a comparison between a selected location value and an expected value in the scan controller. It is yet another feature of the present invention, that the polling operation can be implemented in the scan controller without intervention of the test and debug unit. It is still another feature of the present invention to provide apparatus in the scan controller that permits the value retrieved from a selected location to be compared with the expected value in the scan controller. It would be still another feature of the present invention to provide for a plurality of polling operations by the scan controller in response to a command and expected value from the test and debug apparatus. It is a still further feature of the apparatus and associated method to provide for the polling of a plurality of signals groups in the received data stream in a single operation.